1. Field of the Invention
The present invention relates generally to a data transfer device used for a high speed serial communication apparatus, and more particularly to a data transfer device in which data transfer between blocks having clock domains different from each other is performed in synchronization with a clock signal.
2. Description of Related Art
FIG. 20 is a block diagram showing a conventional data transfer device arranged in a serial communication apparatus. In FIG. 20, a reference sign A indicates a high speed operating block, a reference sign B indicates a low speed operating block, and a reference sign C indicates a clock signal producing block.
Next, an operation of the conventional data transfer device will be described below.
Assuming that protocol processing or signal processing is performed for serial communication data in a high speed serial communication apparatus in synchronization with a clock signal having a frequency equal to or higher than that corresponding to a transmission rate of data, the number of gates serially placed for one cycle of the clock signal in a data transfer device is undesirably increased. Therefore, it is difficult to arrange circuit elements of the data transfer device in the high speed serial communication apparatus.
Therefore, in the data reception performed in the conventional data transfer device shown in FIG. 20, when serial communication data transmitted from the outside is received in the high speed operating block A in synchronization with a clock signal CLK-A having a frequency equal to or higher than that corresponding to a transmission rate of the serial communication data, the serial communication data is converted into parallel data, the parallel data is transferred to in the low speed operating block B, and protocol processing is generally performed for the parallel data in the low speed operating block B in synchronization with a clock signal CLK-B having a frequency lower than that corresponding to the transmission rate of the serial data.
Also, in the data transmission, most of protocol processing is performed in the low speed operating block B for each piece of parallel data, the parallel data is transferred to the high speed operating block A, the parallel data is converted into serial communication data in the high speed operating block A, minimum part of processing is performed for the serial communication data in the high speed operating block A, and the serial communication data is transmitted to the outside.
Because the conventional data transfer device has the above-described configuration, there are following problems.
Because the frequency of the clock signal CLK-A used for the operation of the high speed operating block A differs from the clock signal CLK-B used for the low speed operating block B, data transfer between the operating blocks A and B is asynchronously performed. Therefore, a countermeasure for metastable (or asynchronous data transfer) is required to perform the data transfer between the operating blocks A and B. However, in cases where the countermeasure for metastable is performed in the conventional data transfer device, a problem has arisen that the number of flip-flop circuits (or-registers) in the conventional data transfer device is undesirably increased, electric power consumed in the flip-flop circuits is undesirably increased, gate size is undesirably increased, and internal delay of data is undesirably increased.
Also, in cases where the relation between the clock signal CLK-A of the high speed operating block A and the clock signal CLK-B of the low speed operating block B is expressed according to an equation(Frequency of clock signal CLK-A)=(Frequency of clock signal CLK-B)×(bit length of parallel data), a clock skew between the clock signals CLK-A and CLK-B is adjusted so as to synchronize the clock signal CLK-B with the clock signal CLK-A. In this case, data transfer between the operating blocks A and B can be synchronously performed without performing the countermeasure for metastable. For example, a frequency of the clock signal CLK-A is equal to 480 MHz, a frequency of the clock signal CLK-B is equal to 60 MHz, and a bit length of parallel data is equal to 8 bits. However, it is required to adjust a clock skew between the clock signals CLK-A and CLK-B. Therefore, a problem has arisen that it takes a lot of time to design a data transfer device.
In cases where coding processing such as non-return to zero insert (NRZI) or alternation mark inversion (AMI) coding, coding processing for reception data (RX) and self-synchronization processing are performed for the serial communication data, bit stuffing processing is sometimes performed for the serial communication data for the purpose of the self-synchronization (refer to a literature of “Universal Serial Bus Specification Revision 2.0” pp. 157-158).
In a serial communication apparatus in which self-synchronization is obtained according to the bit stuffing processing, a stuff bit is removed from serial communication data in a data receiving operation, and a stuff bit is inserted into serial communication data in a data transmitting operation. Therefore, in this case, even though the countermeasure for metastable is performed or the clock skew between the clock signals CLK-A and CLK-B is adjusted, data transfer between the operating blocks A and B cannot be synchronously performed.
In the prior art, to synchronously perform data transfer between the operating blocks A and B in the serial communication apparatus in which self-synchronization is obtained according to the bit stuffing processing, following two methods are adopted.
In a first method, the transfer of parallel data RxData and TxData between the operating blocks A and B is controlled in handshaking.
In a second method, the number of stuff bits in the serial transmission data is counted. In a data receiving operation, when the counted value of the stuff bits reaches a bit length of parallel data RxData transferred from the operating block A to the operating block B, a RxValid signal for the parallel data is negated. In this case, the parallel data RxData is treated as invalid data (refer to a literature “USB2.0 Transceiver Macrocell Interface (UTMI) Specification” Ver1.05 page 23 5.6 Bit Unstuff Logic & FIG. 5). In a data transmitting operation, when the counted value of the stuff bits reaches a bit length of parallel data TxData transferred from the operating block B to the operating block A, a TxReady signal is negated to stop the transmission of parallel data TxData from a protocol processing unit of the low speed operating block A (refer to a literature “USB2.0 Transceiver Macrocell Interface (UTMI) Specification” Ver1.05 page 29 5.11 Bit Unstuff Logic & FIG. 11).
However, in these conventional methods, a counter for counting the number of stuff bits or the number of pieces of effective data is required, and logic circuits for producing control signals of data are required. In a circuit operated at a high operating frequency, it is difficult to increase the number of logic circuits placed between flip-flop circuits (or registers). Therefore, a problem has arisen that it is difficult to arrange these logic circuits in a data transfer device. Also, even though these logic circuits can be placed in a data transfer device, a problem has arisen that consumed electric power and gate size in the logic circuits are undesirably increased.